For dense array style circuit layouts, such as static random access memories (SRAMs), a small cell is desired. In a read operation, a bit line and complementary bit line are pre-charged to a supply voltage. An externally received read address signal is decoded, and according to the decoding result, a word line signal for the read operation is enabled. Next, cell access transistors are turned on, and the data stored in the cell is read through the bit line and the complementary bit line. Similarly, in the write operation, a write address signal is received and is decoded, and according to the decoding result, a word line signal for a write operation is enabled, and the access transistors are then turned on, and the data loaded on the bit line and the complementary bit line is stored in the cell.
To avoid over writing data in the cell and thus to increase read stability, an access transistor is usually made weaker than the corresponding pull down devices. In conventional bulk complementary metal oxide semiconductor (CMOS) layouts, the access transistor is designed with a smaller transistor width. In multi gate field effect transistor (MuGFET) technologies, a core cell area is constrained by the distance between two fins (fin pitch) and the number of fins used per device. Thus, fins are placed close together, and are similar in current driving characteristics. One of the characteristics that differentiate MuGFET layouts from convention bulk complementary metal oxide semiconductor (CMOS) layouts is the fixed pitch in which transistor fins must be placed.
One known skinny SRAM cell layout that consumes little area has a length of four fin pitches. pFET (p-type field effect transistor) devices are located in the middle of the layout, with nFET (n-type field effect transistor) devices, including pull down devices located on the sides. The electrical characteristics of this prior SRAM cell are sub-optimal. All the transistors share the same fin height, which is equivalent to the gate width in bulk CMOS. This is not optimal to achieve sufficient cell stability, especially during read and write access.